1. Field of the Invention
The present invention relates to very high frequency phase locked loops (PLLs) and, in particular, to a triangular wave synthesizer that uses a single saw tooth counter to create multiple phase triangular waveforms at greater than original amplitude.
2. Discussion of the Related Art
Commonly-assigned U.S. Pat. No. 5,224,125, issued Jun. 29, 1993, to Hee Wong et al., discloses a signed phase-to-frequency (P-to-F) converter for use in a very high frequency PLL. Referring to FIG. 1, the quasi-digital, high frequency PLL 10 disclosed in the '125 patent includes a phase detector 12, a signed P-to-F converter 14, a 3-phase ring oscillator 16 and a frequency controlled oscillator (FCO) 18. FCO 18 and P-to-F converter 14 allow the use of a clock frequency which is no higher than the generating frequency of the PLL 10 to achieve acceptable phase resolution.
The P-to-F converter 14 converts the phase error information generated by the phase detector 12, which is in the form of UP, DOWN and HOLD signals, to multi-phase analog waveforms (PHASE 1, PHASE 2, PHASE 3) that can be used to drive the FCO 18. The output frequency of the P-to-F converter 14 determines the locking range of the PLL 10. The phase error direction, either plus or minus, is represented by the phase relationship, either leading or lagging, of the multi-phase outputs of the P-to-F converter 14, which the FCO 18 interprets as either an increase, a decrease or no change in the operating frequency.
As shown in FIG. 2, the P-to-F converter 14 disclosed in the '125 patent includes a counting circuit 21 that converts the plus/minus phase error signal UD.sub.-- PI provided by the phase detector 12 into a 7-bit count signal. The three most significant bits (MSB) of the count signal, i.e., the HI.sub.-- CNT signal, are used by a 3-phase waveform generator 25 to generate a 3-phase sawtooth pattern. The four least significant bits (LSB) of the count signal, i.e., the LO.sub.-- CNT signal, are utilized by a pulse density modulation (PDM) circuit 28 to generate a signal that indicates the binary weight of the LSB part of the count. The output of the LSB PDM circuit 28 and the 3-phase sawtooth pattern are applied to three MSB PDM circuits 36, 38, 40. The three carry outputs of the MSB PDM circuits 36, 38, 40 are the digital outputs of the P-to-F converter 14. Following buffering, the three digital outputs of the P-to-F converter 14 are converted to analog signals (PHASE I, PHASE 2, PHASE 3) by RC filters. The plus/minus phase is indicated by the leading/lagging phase relationship among the output waveforms.
While the P-to-F converter 14 disclosed in the '125 patent is a simple, yet elegant solution to a difficult problem, and has been commercially successful, there is always room for improvement. A problem associated with this solution is real time delay. That is, since generation of the triangular waveform is within the PLL tracking loop, the time required for synthesis directly impacts upon the response time of the phase error correction, which increases the phase jitter of the recovered clock.
U.S. Pat. No. 5,224,125 is hereby incorporated by reference in its entirety.